Some of Our Publications

Device Characterization
  1. J.-P. Raskin, G. Dambrine and R. Gillon, “Direct extraction of the series equivalent circuit parameters for the small-signal model of SOI MOSFET’s”, IEEE Microwave and Guided Wave Letters, vol. 7, no. 12, pp. 408-410, December 1997.
  2. J.-P. Raskin, R. Gillon, J. Chen, D. Vanhoenacker, and J.-P. Colinge, “Accurate SOI MOSFET characterisation at microwave frequencies for device performance optimisation and analogue modeling”, IEEE Transactions on Electron Devices, vol. 45, no. 5, pp. 1017-1025, May 1998.
  3. G. Dambrine, C. Raynaud, D. Lederer, M. Dehan, O. Rozeaux, M. Vanmackelberg, F. Danneville, S. Lepilliet and J.-P. Raskin, “What are the limiting parameters of deep-submicron MOSFETs for high frequency applications?”, IEEE Electron Device Letters, vol. 24, no. 3, pp. 189-191, March 2003.
  4. D. Lederer, D. Flandre and J.-P. Raskin, “AC behavior gate transconductance for ultra thin gate oxide PD SOI MOS”, IEEE Electron Device Letters, vol. 25, no. 2, pp. 104-106, February 2004.
  5. D. Lederer, D. Flandre and J.-P. Raskin, “High frequency degradation of body-contacted PD SOI MOSFET output conductance”, Semiconductor Science and Technology, no. 20, pp. 469-472, 2005.
  6. D. Lederer, V. Kilchytska, T. Rudenko, N. Collaert, D. Flandre, A. Dixit, K. De Meyer, and J.-P. Raskin, ”FinFET analog characterization from DC to 110 GHz”, Elsevier Science, Pergamon, Solid-State ElectronicsSpecial Issue, vol. 49, pp. 1488-1496, 2005.
  7. V. Kilchytska, D. Lederer, N. Collaert, J.-P. Raskin and D. Flandre, “Accurate effective mobility extraction by split C-V technique in SOI MOSFETs: suppression of the influence of floating-body effects”, IEEE Electron Device Letters, vol. 26, no. 10, pp. 749-751, October 2005. 
  8. J.-P. Raskin, T.M. Chung, V. Kilchytska, D. Lederer and D. Flandre, “Analog/RF performance of multiple-gate SOI devices: wideband simulations and characterization”, IEEE Transactions on Electron Devices, vol. 53, no. 5, pp. 1088-1094, May 2006.
  9.  J.-P. Raskin, “Wideband characterization of SOI materials and devices”, (invited paper), Elsevier Science, Pergamon, Solid-State Electronics, Special Issue EuroSOI’07, vol. 51, pp. 1161-1171, 2007.
  10. D. J. Pearman, G. Pailloncy, J.-P. Raskin, J. M. Larson and T. E. Whall, “Static and High-frequency behavior and performance of Schottky Barrier p-MOSFET devices”, IEEE Transactions on Electron Devices, vol. 54, no. 10, pp. 2796-2802, October 2007.
  11. D. Lederer and J.-P. Raskin, “Characterization of body node in PD SOI MOSFETs using VNA multiport measurements”, IEEE Transactions on Electron Devices, vol. 54, no. 11, pp. 3030-3039, November 2007.
  12. J.-P. Raskin, D. J. Pearman, G. Pailloncy, J. M. Larson, J. Snyder, D. L. Leadley and T. E. Whall, “High-frequency performance of Schottky Barrier p-MOSFET devices”, IEEE Electron Device Letters, vol. 29, no. 4, pp. 396-398, April 2008.
  13. R. Valentin, E. Dubois, J.-P. Raskin, G. Larrieu, G. Dambrine, Tao Chuan Lim, N. Breil and F. Danneville, “RF small signal analysis of Schottky-Barrier p-MOSFET”, IEEE Transactions on Electron Devices, vol. 55, no. 5, pp. 1192-1202, May 2008.
  14. M. Emam, J. C. Tinoco, D. Vanhoenacker-Janvier and J.-P. Raskin, “High-Temperature DC and RF behaviors of Partially-Depleted SOI MOSFET transistors”, Elsevier Science, Pergamon, Solid-State ElectronicsSpecial Issue, vol52no. 12, pp. 1924-1932, 2008.
  15. J.-P. Raskin, G. Pailloncy, D. Lederer, F. Danneville, G. Dambrine, S. Decoutere, A. Mercha, B. Parvais, “High Frequency Noise Performance of 60 nm gate length FinFETs”, IEEE Transactions on Electron Devices, vol. 55, no. 10, pp. 2718-2727, October 2008.
  16. M. Emam, P. Sakalas, D. Vanhoenacker-Janvier, J.-P. Raskin, T. Lim and F. Danneville, “Experimental Investigation of RF Noise Performance Improvement in Graded-Channel MOSFETs”, IEEE Transactions on Electron Devices, vol. 56, no. 7, pp. 1516-1522, July 2009.
  17. R. Valentin, E. Dubois, J.-P. Raskin, G. Larrieu, G. Dambrine, F. Danneville, “Optimization of RF Performance of Metallic Source/Drain SOI MOSFETs Using Dopant Segregation at the Schottky Interface”, IEEE Electron Device Letters, vol. 30, no. 11, pp. 1197-1199, November 2009.
  18. C. Urban, M. Emam, C. Sandow, Q.-T. Zhao, A. Fox, J.-P. Raskin and S. Mantl, “Small-signal analysis of high-performance of p- and n-type SOI SB-MOSFETs with dopant segregation”, Elsevier Science, Pergamon, Solid-State Electronics, vol. 54, no. 9, pp. 877-882, September 2010.
  19. J.-P. Raskin, J.-P. Colinge, I. Ferain, A. Kranti, C.-W. Lee, N. Dehdashti Akhavan, R. Yan, P. Razavi, R. Yu, “Mobility improvement in nanowire junctionless transistors by uniaxial strain”, Applied Physics Letters, 97, 042114, 2010.
  20. M. Emam, P. Sakalas, D. Vanhoenacker-Janvier, J.-P. Raskin, Tao Chuan Lim, and F. Danneville, “Thermal Noise in MOSFETs: Two or Three-Parameter Noise Model?”, IEEE Transactions on Electron Devices, vol. 57, no. 5, pp. 1088-1091, May 2010.
  21. C. Urban, M. Emam, C. Sandow, J. Knoch, Q. T. Zhao, J.-P. Raskin and S. Mantl, “Radio frequency study of dopant-segregated n-type SB-MOSFETs on thin-body SOI”, IEEE Electron Device Letters, vol. 31, no. 6, pp. 537-539, June 2010.
  22. J. C. Tinoco, A. G. Martinez-Lopez and J.-P. Raskin, “Mobility degradation and transistor asymmetry impact on field effect transistor access resistances extraction”, Elsevier Science, Pergamon, Solid-State Electronics, vol. 56, no. 1, pp. 214-218, February 2011.
  23. M. K. Md Arshad, J.-P. Raskin, V. Kilchytska, F. Andrieux, P. Scheiblin, O. Faynot and D. Flandre, “Extended MASTAR modeling of DIBL in UTB and UTBB SOI MOSFETs”, IEEE Transactions on Electron Devices, vol. 59, no. 1, pp. 247-251, January 2012.
  24. G. Crupi, D. Schreurs, J.-P. Raskin and A. Caddemi, “A comprehensive review on microwave FinFET modeling for progressing beyond the state of art”, (Review Paper), Elsevier Science, Pergamon, Solid-State Electronics, vol. 80, pp. 81-95, 2013.
  25. M. Emam and J.-P. Raskin, “Partially-Depleted SOI versus Deep n-Well Protected Bulk-Si MOSFETs: A High Temperature RF Study for Low Voltage Low Power Applications,” IEEE Trans. on Microwave Theory and Techniques, vol. 61, no. 4, pp. 1496-1504, April 2013.
  26. S. Makovejev, B. Kazemi Esfeh, F. Andrieu, J.-P. Raskin, D. Flandre, and V. Kilchytska, “Assessment of Global Variability in UTBB MOSFETs in Subthreshold Regime”, Journal of Low Power Electronics and Applications, vol. 4, pp. 201-213, 2014
  27. M. K. M. Arshad, S. Makovejev, S. Olsen, F. Andrieu, J.-P. Raskin, D. Flandre, and V. Kilchytska, “UTBB SOI MOSFETs analog figures of merit: effects of ground plane and asymmetric double-gate regime,” Solid State Electronics, vol. 90, pp. 56-64, 2013.
  28. S. Makovejev, B. Kazemi Esfeh, J.-P. Raskin, V. Kilchytska, D. Flandre, V. Barral, N. Planes, and M. Haond, “Variability of UTBB MOSFET Analog Figures of Merit in Wide Frequency Range,” in European Solid-State Device Research Conference ESSDERC, 2014.
  29. S. Makovejev, J.-P. Raskin, D. Flandre, S. Olsen, F. Andrieu, T. Poiroux, and V. Kilchytska, “Comparison of small-signal output conductance frequency dependence in UTBB SOI MOSFETs with and without ground plane,” IEEE 2011 International SOI Conference, Oct. 2011.

 

Substrates
  1. J.-P. Raskin, A. Viviani, D. Flandre and J.-P. Colinge, “Substrate Crosstalk reduction using SOI technology”, IEEE Transactions on Electron Devices, vol. 44, no. 12, pp. 2252-2261, December 1997.
  2. V. Kilchytska, G. Pailloncy, D. Lederer, J.-P. Raskin, N. Collaert, M. Jurczak and D. Flandre, “Frequency Variation of the Small-Signal Output Conductance of Decananometer MOSFETs Due to Substrate Crosstalk”, IEEE Electron Device Letters, vol. 28, no. 5, pp. 419-421, May 2007.
  3. D. Lederer and J.-P. Raskin, “RF performance of a commercial SOI technology transferred onto a passivated HR silicon substrate”, IEEE Transactions on Electron Devices, vol. 55, no. 7, pp. 1664-1671, July 2008.
  4. K. Ben Ali, C. Roda Neve, A. Gharsallah, J.-P. Raskin, “Ultra wide frequency range crosstalk into standard and trap-rich high resistivity”, IEEE Transactions on Electron Devices, vol. 58, no. 12, pp. 4258-4264, December 2011.
  5. C. Roda Neve and J.-P. Raskin, “RF harmonic distortion of CPW lines on HR-Si and trap-rich HR-Si substrates”, IEEE Transactions on Electron Devices, vol. 59, no. 4, pp. 924-932, April 2012.
  6. K. Ben Ali, C. Roda Neve, A. Gharsallah, and J.-P. Raskin, “RF Performance of SOI CMOS Technology on Commercial 200-mm Enhanced Signal Integrity High Resistivity SOI Substrate”, IEEE Transactions on Electron Devices, vol. 61, no. 3, pp. 722-728, March 2014.
  7. K. Ben Ali, C. Roda Neve, A. Gharsallah, and J.-P. Raskin, “Photo-Induced Coplanar Waveguide RF Switch and Optical Crosstalk on High-Resistivity Silicon Trap-Rich Passivated Substrate”, IEEE Transactions on Electron Devices, vol. 60, no. 10, pp. 3478-3484, Oct 2013
  8. K. Ben Ali, C. Roda Neve, A. Gharsallah, J.-P. Raskin, “Efficient polysilicon passivation layer for crosstalk reduction in high-resistivity SOI substrates”, Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF), pp. 212 – 215, Jan. 2010
  9. K. Ben Ali, C. Roda Neve, A. Gharsallah, J.-P. Raskin, “RF SOI CMOS technology on commercial trap-rich high resistivity SOI wafer”, IEEE International SOI Conference, Oct. 2012
  10. C. Roda Neve, K. Ben Ali, C. Malaquin, F. Allibert, E. Desbonnets, I. Bertrand, W. Van Den Daele, J.-P. Raskin, “RF and linear performance of commercial 200 mm trap-rich HR-SOI wafers for SoC applications”, Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF), pp. 15 – 17, Jan. 2013
  11. K. Ben Ali, C. Roda Neve, Y. Shim, M. Rais-Zadeh, J.-P. Raskin, “Non-linear characteristics of passive elements on trap-rich high-resistivity Si substrates”, Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF), pp. 4 – 6, Jan. 2014
  12. K. Ben Ali, C. Roda Neve, A. Gharsallah, J.-P. Raskin, “Digital Substrate Noise Coupling into Trap-Rich HR-SOI Substrate”, EuroSOI, 2013
  13. C. Roda Neve, K. Ben Ali, P. Sarafis, E. Hourdakis, A. G. Nassiopoulou, J.-P. Raskin, “Effect of Temperature on advanced Si-based substrates performance for RF passive integration”, Materials for Advanced Metallization, 2013

 

Self-Heating
  1. S. Makovejev, S. H. Olsen, V. Kilchytska, and J.-P. Raskin, “Time and Frequency Domain Characterization of Transistor Self-Heating,” IEEE Transactions on Electron Devices, vol. 60, no. 6, pp. 1844-1851, 2013.
  2. S. MakovejevJ.-P. Raskin, M. K. Md Arshad, D. Flandre, S. Olsen, F. Andrieu, and V. Kilchytska, “Impact of self-heating and substrate effects on small-signal output conductance in UTBB SOI MOSFETs,” Solid-State Electronics, vol. 71, pp. 93-100, 2012.
  3. S. Makovejev, S. Olsen, and J.-P. Raskin, “RF Extraction of Self-Heating Effects in FinFETs,” IEEE Transactions on Electron Devices, vol. 58, no. 10, pp. 3335-3341, 2011.
  4. V. Kilchytska, M. K. Md Arshad, S. Makovejev, S. Olsen, F. Andrieu, T. Poiroux, O. Faynot, J.-P. Raskin, and D. Flandre, “Ultra-thin body and thin-BOX SOI CMOS technology analog figures of merit,” Solid-State Electronics, vol. 70, pp. 50-58, 2012.
  5. Makovejev, S., Kazemi Esfeh, B., Barral, V., Planes, N., Haond, M., Flandre, D., & Raskin, J.-P. (2014). Wide Frequency Band Assessment of 28 nm FDSOI Technology Platform for Analogue and RF Applications. Ultimate Integration on Silicon, ULIS.
  6. Makovejev, S., Barraud, S., Poiroux, T., Rozeau, O., Raskin, J.-P.Flandre, D., & Kilchytska, V. (2014). Impact of Self-Heating on UTB MOSFET Parameters. EuroSOI.
  7. S. Makovejev, B. Kazemi Esfeh, J.-P. RaskinD. Flandre, V. Kilchytska, “Threshold Voltage Extraction Techniques and Temperature Effect in Context of Global Variability in UTBB MOSFETs”, European Solid-State Device Research Conference ESSDERC, Sep. 2013
  8. S. Makovejev, B. Kazemi Esfeh, F. Andrieu, J.-P. Raskin, D. Flandre, V. Kilchytska, “Global Variability of UTBB MOSFET in Subthreshold”, IEEE SOI-3D-Subthreshold Microelectronics Technology Conference S3S, Oct. 2013
  9. S. Makovejev, S. Olsen, F. Andrieu, T. Poiroux, O. Faynot, D. FlandreJ.-P. Raskin, and V. Kilchytska, “On Extraction of Self-Heating Features in UTBB SOI MOSFETs,” in Ultimate Integration on Silicon, ULIS, 2012.
  10. S. Makovejev, S. H. Olsen, M. K. M. Arshad, D. FlandreJ.-P. Raskin, and V. Kilchytska, “Improvement of High-Frequency FinFET Performance by Fin Width Engineering,” in IEEE International SOI Conference, Oct. 2012.
  11. S. Makovejev, V. Kilchytska, M. K. Md Arshad, D. Flandre, F. Andrieu, O. Faynot, S. Olsen, and J.-P. Raskin, “Self-Heating and Substrate Effects in Ultra-Thin Body Ultra-Thin BOX Devices,” in Ultimate Integration on Silicon, ULIS, 2011.
  12. S. Makovejev, S. Olsen, and J.-P. Raskin, “RF extraction of self-heating effects in FinFETs of various geometries,” in 2011 IEEE 11th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, pp. 117-120, 2011.
  13. S. Makovejev, S. Olsen, M. Dehan, and J.-P. Raskin, “Self-Heating Effect Characterisation in SOI FinFETs,” in Ultimate Integration on Silicon, ULIS, 2010.

 

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